The present invention relates to semiconductor devices, and more particularly to a method and system for controlling the spatial overlap between the source or drain and the gate.
A conventional semiconductor device typically includes a number of cells, each having a source, a drain, and at least one gate. FIG. 1 depicts such a conventional semiconductor device 10. The semiconductor device 10 includes a substrate 11. The semiconductor device includes conventional cells 15 and 17. The conventional cells 15 and 17 include conventional gates 20 and 26, which are separated from the semiconductor substrate 11 by a tunneling barrier 13. Although only a single conventional gate 20 and 26 is shown for each conventional cell 15 and 17, respectively, each conventional cell 15 and 17 may have multiple conventional gates in a gate stack. The conventional gates 20 and 26 are typically formed of polysilicon. Also depicted in FIG. 1 are conventional sources 12 and 16 and a conventional drain 14. As depicted in FIG. 1, the conventional sources 12 and 16 and the conventional drain 14 each has a particular shape. The conventional sources 12 and 16 extend under and have a spatial overlap with the gates 20 and 26, respectively. Similarly, the conventional drain 14 extends under and has a spatial overlap with the conventional gates 20 and 26.
FIG. 2A depicts a conventional method 50 for forming the conventional semiconductor device 10. The method 50 depicted in FIG. 2A will be described in conjunction with FIGS. 2B-2D. Referring to the FIGS. 2A-2D, the tunneling barrier 13 is provided, via step 52. The timing barrier 13 is typically a very thin insulator, often less than 100 Angstroms. In addition, the tunneling barrier 13 may be made of a nitride. Currently, either NO or N2O are often used. The conventional gates 20 and 26 are then provided, via step 54. Step 54 typically includes providing a layer of polysilicon and then defining the conventional gates from the layer of polysilicon. The conventional gates are typically 1500-3000 Angstroms in thickness. FIG. 2B depicts the conventional semiconductor device 10 after the conventional gates 20 and 26 have been defined. An optional halo implant is then typically provided, via step 56. The halo implant typically utilizes the dopants having the same conductivity type as the channel and, therefore, the underlying substrate. Thus, the halo implant has conductivity type as the opposite of the source 12 or 16 and the drain 14. The halo implant is typically provided a high angle, so that will be under the gate and between the source and the drain for a particular memory cell. This angle is depicted by the direction of the arrows in FIG. 2B.
A first conventional source and drain implant, for the extensions of the source and drain, is provided, via step 58. The implant is typically and LDD implant. In some conventional methods 50 the dopant used in step 58 is phosphorus. Also step 58, the first conventional source and drain implant is driven to ensure that the input extends over the desired area. However, typically the step drives the first source and drain implant under the gates. For example, FIG. 2C depicts the conventional semiconductor device 10 after the step 58 has been completed. The portions of the sources 12 and 16 and the portion of the drain 14 formed by the conventional first source and drain implant are depicted by areas 12A, 14A, and 16A. These areas 12A, 14A and 16A are shallow and extend under the conventional gates 20 and 26. Thus, the portions of the areas 12A, 14A and 16A that extend under the gates 20 and 26 are typically called the source extensions and drain extensions.
After the first conventional source and drain implants are provided and driven in step 58, conventional spacers are provided, via step 60. The conventional spacers 22, 24, 26 and 30 are typically on the order of five hundred to one thousand Angstroms in width. After the conventional spacers are provided in step 60, a conventional source and drain implant is provided, via step 62. The conventional source and drain implant provided in step 62 is typically arsenic and use the provided direction perpendicular to the surface of the conventional semiconductor device 10. Because of the presence of the conventional spacers 22, 24, 26 and 30, the dopant for conventional source and drain implants provided in step 62 is spaced apart from the gates 20 and 26 by the width of the spacers 22, 24, 26 and 30. In other words, the dopant for the conventional source and drain implant typically starts out five hundred to one thousand Angstroms away from the conventional gates 20 and 26. Thus, once the dopant for the conventional source and drain implant provided in step 62 is thermally cycled, the dopant is not driven under the conventional gates 20 and 26. FIG. 2D depicts the conventional semiconductor device 10 after step 62 has been formed. The conventional sources 12 and 16 are depicted as having portions 12A and 12B and portions 16A and 16B, respectively. Similarly, the drain 14 is depicted as having portions 14A and 14B. The portions 12B, 14B and 16B are formed in the conventional source and drain implant performed in step 62. Thus, the portions 12B, 14B and 16B are provided after formation of the conventional spacers 22, 24, 28 and 30. As a result, the portions 12B and 14B and the portions 14B and 16B do not extend under the edges of the conventional gates 20 and 26, respectively.
Although the method 50 can be used provided conventional semiconductor device 10, one of ordinary skill in the art will readily realize that there several drawbacks to the conventional semiconductor device 10 so formed. The conventional sources 12 and 16 and the conventional drain 14 extend under the conventional gates 20 and 26. In particular, the extensions of the portions 12A and 14A and the portions 14A and 16A extend under the conventional gates 20 and 26, respectively. In general, the portions 12A, 14A and 16A extend under each of the conventional gates 20 and 26 by approximately eighty to one hundred Angstroms. This spatial overlap between the gates 20 and 26 and the source 12 and 16, respectively, and between the gates 20 and 26 and drain 14 causes several problems.
The spatial overlap between the sources 12 and 16 or the drain 14 in the gates 20 and 26 causes a increased power dissipation by the conventional cells 15 and 17. A leakage current during the off state of the cells 15 and 17 is proportional to the area of spatial overlap between the gates 20 and 26 and the sources 12 and 16 or the drain 14. This leakage current is due to the tunneling of charge carriers between the portions of the conventional sources 12 and 16 under the conventional gates 20 and 26 (i.e. the source and drain extensions) and conventional gates 20 and 26 and to tunneling between the portions of the conventional drain 14 under the conventional gates 20 and 26 the conventional gates 20 and 26. The leakage current is particularly high for low bias devices. The leakage current can drastically increase the power consumed by the conventional semiconductor device 10, which is undesirable.
The spatial overlap between the conventional sources of 12 and 16 and the conventional gates 20 and 26 and between the conventional drain 14 from the conventional gates 20 and 26 can also adversely affect the tunneling barrier 13. Hot carrier injection at the overlap of the source 12 or 16 and the gate 20 or 26 or at the overlap of the drain 14 and the gate 20 or 26 causes stress in the tunnel barrier 13. Consequently, the portion of the barrier 13 above the overlaps can be degraded.
The overlap between the conventional sources 12 and 16, the conventional drain 14 and the conventional gates 20 and 26 can also introduced an additional delay. The spatial overlap regions are capacitive regions. In other words, the conventional gates 20 and 26 are conductive. In addition, the conventional sources 12 and 16 and the conventional drain 14 are conductive. As a result, in the overlap region there are two conductors (the gate 20 and 26 and the source 12 and 16 or the gate 20 and 26 and drain 14) separated by an insulator, the tunneling barrier 13. Consequently, capacitances exist in the overlap regions. These capacitances can introduce an RC delay in the conventional semiconductor device 10. Typically, a high speed is a desired characteristic in semiconductor devices. Consequently, such a delay is undesirable. In addition to the above-mentioned issues, the spatial overlap regions allow for increased band to band tunneling in the gate into stood leakage current.
Furthermore, there may also be and other drawback to the conventional semiconductor device 10. Typically, a high field exists at the corners of the gates 20 and 26. In general, electric fields tended concentrate near sharp corners. When NO or N2O are used for the tunneling barrier 13, the polysilicon gates 12 and 16 have sharp corners because oxidation does not substantially round the corners of the gates 20 and 26 in the presence of the NO or N2O tunneling barriers 13. The high fields concentrated at the corners of the gates 20 and 26 tends to degrade the structure and, therefore, the performance of the conventional semiconductor device 10.
Accordingly, what is needed is a system and method for improving the performance of semiconductor devices, particularly reducing source and drain leakage current. The present invention addresses such a need.
The present invention provides a method and system for providing a semiconductor device on a substrate. The method and system comprise providing a tunneling barrier on the substrate and providing at least one gate on the tunneling barrier. The at least one of gate includes a first edge, a second edge and a base. The method and system further comprise providing a source and/or a drain for the at least one gate. The source and/or a drain are in proximity to the first edge or the first and second edges of the at least one gate. The at least one gate, the source and/or drain or both the at least one gate and the source and/or drain are specially configured such that source and/or drain do not substantially overlap the at least one gate at the base of the at least one gate.
According to the system and method disclosed herein, the present invention reduces the leakage current from the source and/or drain when the power is off. In addition, the present invention may reduce the capacitive delay, the gate induced leakage current, and the band to the band tunneling, and damage due to hot carrier injection.